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MC74HCT245A Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC74HCT245A is identical in pinout to the LS245. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The MC74HCT245A is a 3-state noninverting transceiver that is used for 2-way asynchronous communication between data buses. The device has an active-low Output Enable pin, which is used to place the I/O ports into high-impedance states. The Direction control determines whether data flows from A to B or from B to A.
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PDIP-20 N SUFFIX CASE 738 1
* * * * * * * *
Output Drive Capability: 15 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 V to 5.5 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 304 FETs or 76 Equivalent Gates Pb-Free Packages are Available
A1 A2 A DATA PORT A3 A4 A5 A6 A7 A8 DIRECTION 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 B DATA PORT
SOIC-20W DW SUFFIX CASE 751D 1
TSSOP-20 DT SUFFIX CASE 948E 1
SOEIAJ-20 F SUFFIX CASE 967 1
PIN ASSIGNMENT
DIRECTION A1 A2 Units ea ns mW pJ A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OUTPUT ENABLE B1 B2 B3 B4 B5 B6 B7 B8
OUTPUT ENABLE
PIN 20 = VCC PIN 10 = GND
Figure 1. Logic Diagram
Design Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product *Equivalent to a two-input NAND gate. Value 76 1.0 5.0 0.005
FUNCTION TABLE
Control Inputs Output Enable L L H X = Don't Care Direction L H X Operation Data Transmitted from Bus B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (High-Impedance State)
ORDERING INFORMATION
See detailed ordering, shipping information, and marking information in the package dimensions section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
January, 2007 - Rev. 10
Publication Order Number: MC74HCT245A/D
MC74HCT245A
I I II IIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, PDIP SOIC Package TSSOP Package Storage Temperature mW Tstg TL - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Secs (PDIP, SOIC, SSOP or TSSOP Package)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
II I I I II I I IIIIIIIIIIIIIIIIIIIIIII I II I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIII I I II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I
Symbol VCC Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout TA VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) - 55 0 + 125 500 _C ns tr, tf
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MC74HCT245A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
IIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III IIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIII I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII I II I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I III I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I
Guaranteed Limit v 85_C 2.0 2.0 0.8 0.8 4.4 5.4 Symbol VIH VIL Parameter Test Conditions VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 5.5 - 55 to 25_C 2.0 2.0 0.8 0.8 4.4 5.4 v 125_C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 Unit V V V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 6.0 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 6.0 mA Maximum Low-Level Input Voltage VOH Minimum High-Level Output Voltage 3.98 0.1 0.1 3.84 0.1 0.1 VOL Maximum Low-Level Output Voltage V 0.26 0.33 Iin Maximum Input Leakage Current Vin = VCC or GND, Pins 1 or 19 0.1 4.0 1.0 40 1.0 160 mA mA mA ICC IOZ Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current Vin = VCC or GND Iout = 0 mA Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND, I/O Pins 0.5 5.0 10 DICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 mA -55_C 2.9 25_C to 125_C 2.4 5.5 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit v 85_C 28 36 36 15 10 15
Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH
Parameter
- 55 to 25_C 22 30 30 12 10 15
v 125_C 33 42 42 18 10 15
Unit ns ns ns ns
Maximum Propagation Delay, A to B or B to A (Figures 2 and 4)
Maximum Propagation Delay, Direction or Output Enable to A or B (Figures 3 and 5) Maximum Propagation Delay, Output Enable to A or 8 (Figures 3 and 5) Maximum Output Transition Time. any Output (Figures 2 and 4) Maximum Input Capacitance (Pin 1 or 19)
tTLH, tTHL Cin
pF pF
Cout
Maximum Three-State I/O Capacitance, (I/O in High-Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 97 pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HCT245A
SWITCHING WAVEFORMS
INPUT A OR B OUTPUT B OR A
tr 2.7 V 1.3 V 0.3 V tPLH 90% 1.3 V 10% tTLH
tf
3.0 V
tPHL
GND
tTHL
Figure 2.
DIRECTION
1.3 V
1.3 V
3.0 V GND 3.0 V
OUTPUT ENABLE
1.3 V tPZL 1.3 V tPZH tPHZ tPLZ 10% 90%
GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
A OR B A OR B
1.3 V
Figure 3.
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST
TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5. Test Circuit
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MC74HCT245A
A1
2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B8 B7 B6 B5 B4 B DATA PORT B3 B2 B1
A2
A3
A DATA PORT
A4
A5
A6
A7
A8
DIRECTION
1
OUTPUT ENABLE
19
Figure 6. Expanded Logic Diagram
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MC74HCT245A
ORDERING INFORMATION
Device MC74HCT245AN MC74HCT245ANG MC74HCT245ADW MC74HCT245ADWG MC74HCT245ADWR2 MC74HCT245ADWR2G MC74HCT245ADT MC74HCT245ADTG MC74HCT245ADTR2 MC74HCT245ADTR2G MC74HCT245AFELG Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* SOEIAJ-20 (Pb-Free) 2500 / Tape & Reel 2000 / Tape & Reel 75 Units / Rail 1000 / Tape & Reel 38 Units / Rail 18 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb-Free.
MARKING DIAGRAMS
PDIP-20 20 20 MC74HCT245AN AWLYYWWG 1 1
SOIC-20W
HCT245A AWLYYWWG
TSSOP-20 20 HCT 245A ALYWG G 1 1 20
SOEIAJ-20
74HCT245A AWLYWWG
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
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MC74HCT245A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
SOIC-20W DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74HCT245A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE C
20X
K REF
M
2X
L/2
20
11
J J1 B
L
PIN 1 IDENT 1 10
-U- N
0.15 (0.006) T U
S
A -V-
N F DETAIL E
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT
7.06 1
16X
0.36
16X
1.26
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HCT245A
PACKAGE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC74HCT245A/D

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